1. Technical Field
Embodiments of the inventive concept relate to a clock generator used in a display driver, and more particularly, to a clock generator to reduce long term jitter.
2. Discussion of Related Art
A digital signal converted from an analog video signal may be reproduced through corresponding pixels of an image to generate a viewable image corresponding to the analog video signal. A pixel clock signal may be used to temporally and spatially reproduce the digital signal converted from the analog video signal. The pixel clock signal may be synchronized with a horizontal synchronous signal and have a specific frequency and phase. The pixel clock signal may be generated by a pixel clock generator. The pixel clock generator may use a phase locked loop (PLL), which includes a charge pump PLL circuit and a digital PLL circuit. A PLL is a control system that generates a signal that has a fixed relation to the phase of a reference signal. A PLL responds to both the frequency and the phase of the input signals, automatically raising or lowering the frequency of a controlled oscillator until it is matched to the reference in both frequency and phase.
If the pixel clock signal generated by the pixel clock generator does not have a regular phase, an image reproduced by using the pixel clock signal may not be properly displayed. An irregular phase of the pixel clock signal may be caused by long term jitter. For a charge pump PLL, which generates a high frequency signal by using a low frequency signal, long term jitter may be generated due to leakage current generated from the charge pump PLL when a metal line pitch is reduced to decrease the circuit area and power consumption. The digital PLL circuit may remove the long term jitter generated in the charge pump PLL circuit and reduce the circuit area and power consumption. However, the digital PLL circuit may have a large number of transistors as compared to the charge pump PLL circuit, and thus phase noise increases and 1/f noise generated from a digitally controlled oscillator included therein also increases. Further, the dynamic range (e.g., the ratio between the smallest and largest possible values of a changeable quantity) of a signal output from the digital PLL circuit is restricted, and thus a jitter component is generated.